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Design Verification Engineer

Company: ASICSOFT
Location: Roseville
Posted on: March 27, 2020

Job Description:

Design Verification Engineer Roseville, CA 9 month Contract IMPORTANT Manager wants a DV engineer that has some RTL experience doing some design Some Protocol knowledge with any 1 of these is required TCPIP, SCSI, Fiber Channel, Ethernet, SAS, SATA, RDMA protocols PCIe Job must be done in Roseville location, NO REMOTE WORK REQUIREMENTS 10 or more years experience in design, implementation and verification of storage andor networking Strong communication skills, both verbal and written Proficiency with Verilog System Verilog RTL coding and verification Proficiency with UVM strongly desired Familiarity with synthesis and static timing Experience with FPGA flows and the Xilinx andor Altera toolset helpful Experience in architecting test bench environments for unit and system level verification Protocol knowledge in one or more of the following areas TCPIP, SCSI, Fiber Channel, Ethernet, SAS, SATA, RDMA protocols PCIe Proven track record with writing detailed test plans Problem solving skills and out-of-the-box thinking to test and validate RTL RESPONSIBILITIES RTL Design RTL Verification Micro-architecture Documentation RTL Coding RTL Verification Verification environment, coding and test writing System testing and debug using FPGAs Debugging (e.g. PCIe, Network Protocol and Logic Analyzers) Scripting Test plan documentation

Keywords: ASICSOFT, Roseville , Design Verification Engineer, IT / Software / Systems , Roseville, California

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