ASIC Design & Verification Engineer
Company: HCL Global Systems
Location: Roseville
Posted on: March 14, 2020
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Job Description:
Title ASIC Design Verification Engineer Location Roseville, CA
Duration Fulltime JD 10+ years of RTL Design (Verilog) and
Verification experience (SV, UVM) combined exp Experience on Micro
architecture and interface protocols (PCIe, USB, SATA, Ethernet
etc. any one) Experience in Test planning, Test bench, environment
etc. Can do functional and code coverage Have worked on module and
top level verification for SoC Thanks Regards Srinivas HCL Global
Systems, Inc Phone 248-473-0720 Ext 169 Email Id
Keywords: HCL Global Systems, Roseville , ASIC Design & Verification Engineer, IT / Software / Systems , Roseville, California
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