Video Codec Design Verification Engineer - 100605
Posted on: January 13, 2022
What You Do At AMD Changes Everything
At AMD, we push the boundaries of what is possible. We believe in
changing the world for the better by driving innovation in
high-performance computing, graphics, and visualization
technologies - building blocks for gaming, immersive platforms, and
the data center.
Developing great technology takes more than talent: it takes
amazing people who understand collaboration, respect, and who will
go the "extra mile" to achieve unthinkable results. It takes people
who have the passion and desire to disrupt the status quo, push
boundaries, deliver innovation, and change the world. If you have
this type of passion, we invite you to take a look at the
opportunities available to come join our team.
Video Codec Design Verification Engineer
We, the VCN (Video Codec Next) IP team, are based in Markham, ON,
Canada! We focus on video codec IP development for AMD SOCs with
leading ASIC technology. We are looking for a self-motivated,
experienced verification engineer in the Folsom, CA, area to
complement our team to develop world class video solutions verified
to the highest standards.
You are encouraged to actively collaborate with various team
members to understand design requirements, drive block-level
verification, support IP level integration and verification, and
pursue functional and code coverage closure linked back to
requirements throughout the design cycle. Proven technical skills,
and excellent communication skills working in remote teams are key
factors to make you successful in this group.
- Draft block-level verification plans with functional coverage
- Construct block-level testbenches using UVM.
- Devise and implement block-level tests, and handle regression
suites with performance and scalability considerations
- Triage test run failures and provide debug support to design
engineers to isolate the causes.
- Actively drive simulation efficiency profiling and use
state-of-the-art practices to help optimize regression turnaround
- Own verification of the design across multiple abstractions and
views, including C-model simulation, RTL simulation and formal
- Ensure the design can meet performance targets with accurate
modeling of interface protocol behavior in the block-level
testbenches in aligned with IP level behavior with top-down
- Conduct coverage analysis, profiling, and reporting, and
augment test suites towards coverage improvements and
- Support IP-level feature integration and bring-up of RTL blocks
and assist in IP-level simulation debug. Preferred Experience:
- Minimum 3 years of proven ASIC/FPGA design verification
- Rich knowledge of ASIC design flow from specification to
implementation and verification.
- Proficient in UVM.
- Strong in SystemC, C++/C programming.
- Proven knowledge of Verilog RTL design.
- Experience with HLS flow in sophisticated design implementation
and verification is a definite asset
- Familiar with simulation CAD tools including coverage reporting
- Handy in Linux scripting languages such as Perl, Python, Ruby
and/or shell languages.
- Solid problem-solving skills.
- Prior team or technical leadership, or mentorship, are great
- Excellent teammate and communicator
- Basic video codec knowledge is a definite plus. Academic
Minimum Bachelor of Science Degree in Electrical Engineering,
Computer Science, or Computer Engineering.
AMD employees who will be working onsite at an AMD US facility, are
encouraged to provide proof of being fully vaccinated against
COVID-19 upon their start date. This is for the safety of our
employees, and to permit AMD to be prepared in the event the stay
on Executive Order 14042: Ensuring Adequate COVID Safety Protocols
for Federal Contractors is lifted. AMD is not requiring exemption /
accommodation submittals at this time.
Requisition Number: 100605
Country: United States State: California City: Roseville
Job Function: Design
Hiring Manager: Sean Xu
AMD does not accept unsolicited resumes from headhunters,
recruitment agencies or fee based recruitment services. AMD and its
subsidiaries are equal opportunity employers. We consider
candidates regardless of age, ancestry, color, marital status,
medical condition, mental or physical disability, national origin,
race, religion, political and/or third party affiliation, sex,
pregnancy, sexual orientation, gender identity, military or veteran
status. Please click here for more information.
Keywords: AMD, Roseville , Video Codec Design Verification Engineer - 100605, Engineering , Roseville, California
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